(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a capacitor that avoids problems of high etch selectivity and the presence of remnants of salicided material and that reduces the potential for shorts between the plates of the capacitor.
(2) Description of the Prior Art
The majority of the functions that are performed by semiconductor devices are functions of data manipulation or logic functions, these functions are mostly related to digital data manipulation but do not exclude the functions of analog data manipulation. Many of these functions depend on and make use of data retention, these data retention functions are performed by semiconductor memory devices. Two types of memory devices can be identified, that is memory functions that retain data in storage cells from which the data can only be read (Read Only Memories or ROM's) or memory functions whereby the data cannot only be read but can also be altered (Random Access Memories or RAM's).
The latter category of memory devices has been created using a number of different approaches, resulting in different types of RAM devices. Distinguished can be for instance the Dynamic RAM (DRAM), which uses capacitors as the storage medium and which are therefore, due to the non-permanent nature of capacitive storage, periodically refreshed, and the Static RAM (SRAM) which depends on the presence of a power source for the retention of the stored data. DRAM memories offer advantages of economy of construction and of relatively high storage capabilities and have therefore attracted a great deal of attention in the semiconductor industry. DRAM memory is typically created by creating a multiplicity of memory cells arranged in matrix form. Each cell comprises a storage capacitor and a gate electrode type transistor, which is connected in series with other memory cells of the DRAM cell configuration. Word lines and bit lines provide the functional capability of the DRAM memory cell, the transistor of the DRAM cell is connected to the word line while the bit lines are connected to a sense amplifier. The word lines and bit lines intersect under an angle of ninety degrees. The capacitive charge is accessed or read from the cell by activating the word line and the sense amplifier, which results in the capacitive charge to be read by the bit line of the CRAM cell. The capacitive charge is then further amplified by the sense amplifier, resulting in either a zero or a one voltage level provided by the sense amplifier.
One of the critical components in the creation of DRAM memory cells is the capacitor. Is it required that the capacitor has a high storage retention, is impervious to noise and does not require an excessive amount of surface area. To address these concerns, different arrangements have been proposed for the creation of the capacitor of a DRAM cell. One such arrangement provides a stacked capacitor. The memory cell under this arrangement comprises one transfer gate transistor and one stacked type capacitor. The transfer gate transistor comprises a pair of source/drain regions formed in a surface of a silicon substrate and a gate electrode (word line) that is formed on the surface of the silicon substrate with an insulation layer interposed therebetween. The stacked type capacitor comprises an underlying electrode (storage electrode) which extends from a position above the gate electrode to a position above a field isolation film, a part of the capacitor is connected to one of the source/drain regions of the gate electrode. A dielectric layer is formed on a surface of the underlying electrode and an upper electrode (cell plate) is formed on a surface of a dielectric layer. A bit line is formed on the capacitor with an interlayer insulation layer interposed therebetween, the bit line is connected to the other source/drain regions of the transfer gate transistor through a bit line contact portion. The stacked type capacitor is characterized in that capacitance of a capacitor is assured by providing the main part of the capacitor extending above the gate electrode and the field isolation film, this to increase an area where the electrodes of the capacitor are opposed to each other.
Another arrangement of a memory cell comprises a so-called cylindrical stacked type capacitor. A transfer gate transistor comprises a gate electrode (word line) with a periphery that is covered with an insulation layer. A word line with a periphery that is covered with the insulation layer is formed on the surface of a shield electrode which is formed on a surface of a silicon substrate with a shield gate insulation film interposed therebetween. An underlying electrode of the capacitor comprises a base portion (formed on a surface of an insulation layer covering surfaces of the gate electrode) and a word line with a cylindrical portion extending vertically and upwardly from the surface of the base portion in the form of a cylinder. A dielectric layer and an upper electrode are sequentially deposited on a surface of a lower electrode. The cylindrical portion of the capacitor can be used as a region for storing electric charges, enabling the capacitance of the capacitor to be increased without increasing the plane of the capacitor.
For purposes of processing efficiency it is desirable to integrate the creation of a capacitor as part of a DRAM cell with processing steps that form the overall DRAM cell. While the creation of the capacitor of the DRAM cell forms part of the overall processing stream, a number of these processing steps are dedicated to the creation of the capacitor of the DRAM cell. A prior art processing sequence that simultaneously creates a MOS gate electrode and a polycide to polysilicon capacitor is shown in FIGS. 1a through 1c. Active surface regions in the surface of substrate 10 are defined by means of the field oxide insulation regions 12 and 13, FIG. 1a. The gate electrode 14 is formed of a layer 20 of polysilicon overlying a layer 18 of pad oxide, the top layer 22 is a salicided layer for reduced contact resistance with the gate electrode 14. Source region 26 and drain region 28 impurity implants (comprising LDD regions 25 and 27 respectively) have been provided in the surface of substrate 10 as have gate spacers 24 for improved insulation of the gate electrode 14.
It is well known in the art that, to reduce contact resistance with the points of electrical contact of the gate electrode, these contact regions are salicided. This is accomplished by forming a silicide film of a metal that has a high melting point on these surfaces. A titanium silicide film is frequently used as a high melting point silicide film while cobalt silicide and nickel silicide film have also been investigated. The basic success of forming salicided contact layers can be achieved due to the fact that certain metals, such as titanium or cobalt, react when heated while they are in contact with silicon. This reaction forms conductive suicides over the surface of the silicon while the metal however does not react with silicon oxides. By forming silicon oxide spacers on the sidewalls of the gate electrode, the deposited metal does not interact with the sidewalls of the gate electrode and separate points of electrical contact can be formed for the source/drain regions and the surface of the gate electrode.
Referring back to FIG. 1a, capacitor 16 is being formed on the surface of the field oxide isolation region 13. The lower plate 30 of capacitor 16 is patterned at the same time at the gate electrode 20. Salicided layer 32 is formed at the same time that the salicided layer 22 is formed on the surface of gate electrode 14. Salicided layer 32 forms the bottom plate of the capacitor and is created following the same considerations that have previously been highlighted for the formation of layer 22.
Referring now to FIG. 1b, there is shown in cross section of capacitor 16 after consecutively a layer 34 of tetra-ethyl-ortho-silicate (TEOS) and a layer 36 of titanium nitride have been deposited over the surface of the isolation region 13 thereby including the surface of salicided layer 32.
From the cross section that is shown in FIG. 1c it can be concluded that prior art method of creating a capacitor as part of a DRAM cell comprises:
using salicided poly as the bottom plate of the capacitor, layer 32 of FIG. 1c PA1 using TEOS as the dielectric material for the capacitor, layer 34 of FIG. 1c PA1 using titanium nitride (TiN) for the top pate of the capacitor, layer 36 of FIG. 1c. PA1 the etching of the upper layer 36 of TiN is a challenge in view of the need for a highly selective etch of layer 36 with respect to the underlying layer 34 of TEOS. Lack of this selectivity in etching layer 36 results in damage to the underlying layer 34 of TEOS, affecting the integrity of dielectric layer of the capacitor and therewith affecting the performance and reliability of the capacitor, and PA1 the process of salicidation that is applied for the creation of layer 32 is prone to leave salicided material in place; this material is typically difficult to completely remove from the surface in view of the metallic nature of the salicided material. The presence of these remnants, also referred to as salicide stringers since these remnant typically have the form of extended, thin metallic strings, is prone to cause electrical shorts through the deposited layer of TEOS, shorting the lower plate 32 with the upper plate 36.
Problems are encountered with this method of creating the capacitor of the DRAM cell, these problems can be summarized as follows:
The invention provides a method that eliminates the above highlighted disadvantages.
U.S. Pat. No. 6,110,791 (Kalnitsky et al.) shows a capacitor where the capacitor dielectric is etched away to form air gaps.
U.S. Pat. No. 6,140,200 (Eldridge) shows a method for a capacitor with air gaps.
U.S. Pat. No. 6,143,618 (Chen et al.), U.S. Pat. No. 6,124,199 (Gainbino et al.), U.S. Pat. No. 5,641,702 (Imai et al.) teach related capacitors.